17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs
As the demand for high-frequency DDR SDRAM increases, duty-cycle correction circuits (DCC) become a key element to widen the data-valid window (tDV). For duty detection in a DCC, analog schemes using charge pumps  and digital schemes using DLL locking  or time-to-digital converters (TDC)  are widely used. However, they require a certain amount of time proportional to duty errors or a high-resolution TDC to resolve quantization errors. For correction, an edge combiner or slew-rate-changing inverter is commonly used in DRAM applications. An edge combiner utilizes 180°-phase-shifted clocks, which are obtained by DLL locking or TDC code calculation [4-5], to generate both edges, but it has high-frequency limitations due to gate-delay-based short-pulse generation. The slew-rate-changing inverter has trade-offs between range and resolutions or between resolutions and DCC locking time. To achieve both wide range and fast locking, asynchronous binary search for detection and receiver tail-current tuning can be used for correction .
In a WCK-based system, duty and phase skew between iclk and qclk are related to the detection range. However, for normal DDR DRAM, this range should be doubled resulting in more area as well as locking time. To resolve problems with locking time, coverage, and resolution, a hybrid DCC is presented in this paper. For precise duty error detection, the phase and DCC locking processes should be separated, because delay updating disturbs duty-error detecting and averaging. In this paper, an all-digital DCC with TDC and an enhanced edge combiner performs fast DCC operation before DLL coarse locking, and a slew-rate-changing DCC optimized for fine resolution compensates quantization errors caused by all-digital operation.