A Resource-Efficient Hardware Architecture for Connected Components Analysis

A resource-efficient hardware architecture for connected components analysis (CCA) of streamed video data is presented which reduces the required hardware resources especially for larger imagewidths. On-chip memory requirements increase with image width and dominate the resources of state-ofthe- art CCA single-pass hardware architectures. A reduction of on-chip memory resources is essential to meet the ever increasing image sizes of high-definition and ultra-high-definition standards. The proposed architecture is resource-efficient due to several innovations. An improved label recycling scheme detects the last pixel of an image object in the video stream only a few clock cycles after its occurrence, allowing the reuse of a label in the following image row.

The coordinated application of these techniques leads to significant memory savings of more than two orders in magnitude compared to classical two-pass connected component labelling architectures. Compared to the most memory-efficient state-of-the-art single-pass CCA hardware architecture, 42% or more of on-chip memory resources are saved depending on the features extracted. Based on these savings, it is possible to realise an architecture processing video streams of larger images sizes, or to use a smaller and more energy-efficient FPGA device, or to increase the functionality of already existing image processingpipelines in reconfigurable computing and embedded systems.