A Speed-Enhancing Dual-Trial Instantaneous Switching Architecture for SAR ADCs

A single-channel asynchronous successive approximation register analog-to-digitalĀ converter with a dual-trial instantaneous switching scheme is presented in this brief. The proposed architecture uses two capacitiveĀ digital-to-analog converter (DAC) arrays to generate two possible outputs while the comparator is in the regenerationĀ process. Two comparators are assigned to each DAC to alternately switch between the compare phase and the reset phase.

Such an approach allows the overlapping of the DAC settling, the comparator reset, and the comparator regeneration, which significantly improves the conversion speed. Furthermore, the random nature of the internal channel selection converts the mismatches between both channels into wideband noise, which improves the spurious-free dynamic range.