An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications

Similarity measures are used in diverse signal-processing applications. Bhattacharyya coefficient is one of the most popular similarity measures that is widely used in many image/video processingapplications. Several of these applications need to compute similarity measure between probability density functions of local image statistics. In this paper, an efficient hardware architecture is proposed for accelerating the local similarity measure (LSM) computation using Bhattacharyya coefficient. Direct hardware implementation of Bhattacharyya coefficient requires many compute-intensive hardware resources, which slow down the overall computation process.

Data path of the proposed architecture utilizes fixed-point arithmetic and is based on the logarithmic number system. Fast binary logarithmic and antilogarithmic computing units are deployed to realize the required complex arithmetic operations. The histogram computation is accomplished using single-cycle read-modify-write operations on the received image data stored in DDR2 SDRAM. The proposed architecture is realized in the Virtex-5 xc5vfx70t FPGA device of Xilinx ML-507 platform. The device utilization of the implemented architecture shows that it utilizes 4.5% FPGA slices, 5.4% Block RAMs and 27.34% DSP48E slices.