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Analog Domain Signal Processing-Based Low-Power 100-Gb/s DP-QPSK Receiver

Coherent techniques are expected to be used to meet the demand for higher data rates in short-reach optical links in the near future. Digital coherent receivers used for long haul applications are not suitable for short-reach links because of excessive power dissipation, size, and cost. The power consumption, size, and cost of the receiver can be drastically reduced by processing signals in the analog domain itself.

A 100 Gb/s dual-polarization quadrature phase-shift keying receiver that uses analog domainsignal processing is presented. The receiver, designed in 130-nm BiCMOS technology, consumes 3.5 W of power. Simulations show bit error rates of less than $10^{-3}$ in the presence of dispersion up to 160 ps/nm, laser linewidths of up to 200 kHz, and a frequency offset of 100 MHz between the transmitter and the receiver lasers.