Recent advances in synthesis tools as well as the use of MATLAB/SIMULINK as a high-level language make it feasible for rapid and efficient verification of Hardware Description Language (HDL) designs. The power of MATLAB in handling complex digital signal processing (DSP) algorithms has strengthened, in one hand, the abilities of processing algorithms for multimedia applications such as video processing. On the other hand, SIMULINK enabled the communication possibilities with HDL simulators which handles DSP algorithms implemented on FPGA. The combination of bothMATLAB/SIMULINK in co-simulation with HDL simulators make it feasible for efficient and real-time verifications where researches are able to verify and debug design errors in simple and efficient way. Advanced digital video coding is one of the most important tools for handling videos with its extensive usage in wide range of applications nowadays. The massive widespread of digital video contents has been driven by the high compression of digital contents with high video quality and low bit rate.
Motion estimation is the key behind such impressive performance. However, high computations with huge memory references are the cost. To compensate for such high cost, hardware implementations of different fast motion estimation algorithms are proposed instead of software solutions. The verification process of such hardware implementations should be flexible and capable of locating and identifying design errors and bugs. In this paper, a methodology for verifying real-time motion estimation based onMATLAB/Simulink co-simulation with an HDL simulator is presented. The methodology aims to improve the verification process of motion estimation as a complex digital system.