SFF-8431 12.5Gbps channel return loss (RL) failure debug: Simulation and measurement validation
The process of troubleshooting a 12.5Gbps SFF-8431 channel return loss compliance failure is described in details. Excellent simulation to measurement correlation has been achieved after capturing a capacitive dip at the package/PCB interface (“phantom” capacitance) with package and board physical layout geometries merged into one single electromagnetic simulation.
Source of the “phantom” capacitance is identified and explained. Design techniques to circumvent the “phantom” capacitance and their effectiveness are evaluated through simulation studies and measurements.