A 2-D massively parallel, high throughput, systolic array for a spatio-temporal wave-digital filter (WDF) architecture is proposed. RF receive mode aperture beam personalities are achieved using 2-D fan filters with dynamically steerable passband directions and fan angles. The wave-digital realization results in low sensitivity of the far-field beam to errors in filter coefficients due to fixed-point effects in the digital arithmetic hardware. A fixed-point design of the systolic-array architecture that eliminates overflow errors is described.
The architecture is implemented in FPGA-prototype form and tested usingMATLAB Simulink with Xilinx EDA tools. The verified digital design is ported to CMOS standard-cell technology to obtain the area and power costs as well as the operational frequency. The 45 nm CMOS synthesis, placement, and routing show overflow free maximum frequency of operation of 131.02 MHz for 1-passband fan filter and an estimated power consumption of 450.30 mW at DC supply voltage 1.1 V indicating potential applications in the VHF range.